The present invention relates, generally, to memory systems. More particularly, the present invention relates to a regulated predriver for an output buffer, such as may be utilized for memory applications.
In the efforts for optimizing power consumption in various high-speed microcontroller-based devices, such as portable personal computers (PCs), personal digital assistants (PDAs) and the like, significant attention has been given to the further improvement of battery life. One area where battery life has been increased is through the development of improved memory devices.
For example, most new microprocessor-based applications that are configured for high processing speed now implement synchronous, dynamic random access memory (SDRAM) devices that can operate at significantly higher clock speeds than conventional memory devices. SDRAM devices are synchronized with the clock speed in which the microprocessor is optimized, thus enabling the number of instructions that the microprocessor can perform at a given time to be increased. Testing has demonstrated that a 25% to 30% increase in battery life can result from increasing the quantity of SDRAM devices in a portable computer system. This result is due mainly to the reduction in use of the hard drive that tends to deplete the battery life.
In the manufacture of SDRAM devices, a further reduction in process geometries has been made in an attempt to manufacture more SDRAM devices per semiconductor wafer. This reduction in SDRAM process geometries has resulted in a further scaling down of internal operating voltages that may be used in output buffer devices. However, external power supply specifications have remained at higher levels for such output buffers.
For example, with reference to FIGS. 1A and 1B, an output buffer 100 as may be implemented within an SDRAM device comprises a control logic and pull-up predriver circuit 102 for controlling and driving a pull-up transistor and a control logic and pull-down predriver circuit 104 for controlling and driving a pull-down transistor. The pull-up transistor can comprise either a p-channel transistor MP0 (FIG. 1A) or an n-channel transistor MN0 (FIG. 1B), while the pull-down transistor can comprise an n-channel transistor MN2. Pull-up transistors MP0 and MN0 and pull-down transistor MN2 are further connected to a bondpad 106. Control logic and predriver circuits 102 and 104 can be configured with an internally supplied voltage VCCR to drive the gates of pull-up transistors MP0 and MN0 and pull-down transistor MN2.
In older predriver schemes, the internally regulated voltage VCCR comprises approximately 2.5 volts. However, as a result of shrinking process geometries, a lower internally regulated voltage VCCR comprising approximately 1.8 volts can be required. At this lower level of internally regulated voltage VCCR, pull-down transistor MN2 must be made large enough to meet the I/O current specifications for DC operation, e.g., a larger output pull-down transistor MN2 is required to meet the external power supply specifications of 3.0 to 3.6 volts for SDRAM devices. In addition, pull-down transistor MN2 must be configured to address the AC access and hold timing considerations. Further, since silicon area is at a premium under current manufacturing conditions, it is highly preferable to drive the gate of output pull-down transistor MN1 with a significantly higher voltage supply.
With reference to FIG. 2, the current-voltage (IV) curves for the input/output current specifications for output pull-down transistor MN1 for an output buffer 100 include a curve 202 representing the maximum driver sink current (IOL) specification and a curve 204 representing the minimum driver sink current (IOL) specification. IOL is a DC specification for the amount of current that output buffer 100 will sink when driving a low (0) signal on bondpad 106, i.e., when a low signal voltage is forced at bondpad 106 while pull-down transistor MN2 is turned on.
In order to meet the minimum IOL current specification, output pull-down transistor MN2 is sized such that an IOL current characteristic 208 will exceed the minimum IOL current specification 204 under lowest input/output conditions, i.e., higher temperature, lower IDS process corner, and lower voltage VCCQ, while also being sized such that an IOL current characteristic 206 will not exceed the maximum IOL current specification 202 under highest input/output conditions, i.e., lower temperature, higher IDS process corner, higher voltage VCCQ. As is evident from FIG. 2, in the event the gate voltage of output pull-down transistor MN2 is not limited, e.g., allowed to increase to 3.6 volts, the current/voltage characteristics of output pull-down transistor MN2 approaches the maximum IOL current specification 202, or even exceeds under worst case conditions.
Thus, in the newer, lower internally regulated voltage schemes, a larger output pull-down transistor MN2 is required to meet AC and DC specifications, which comes at a cost of silicon area. Further, a significantly larger pull-down transistor MN2 increases the difficulty in meeting the maximum output specifications for output buffer 100. Moreover, if the voltage for driving the gate of output pull-down transistor MN2 is level shifted upwards to the external voltage VCCQ of 3.6 volts, then output pull-down transistor MN2 can be suitably overdriven to exceed maximum IOL current specification 202.
In accordance with various aspects of the present invention, a memory system includes an improved predriver circuit for an output buffer that can enable the output buffer to operate well within maximum and minimum IOL current specifications at lower internally regulated voltages. In accordance with an exemplary embodiment, the predriver circuit comprises one or more predriver devices and a regulated limiter circuit configured to limit or otherwise regulate the maximum gate voltage provided to the gate of an output pull-down element. As a result, the device size of the output pull-down element can be optimized to provide additional margin to exceed the minimum IOL specification, while also improving the margin under the maximum IOL specification.
In accordance with an exemplary embodiment, the pull-down predriver circuit comprises one or more predriver elements, e.g., a p-channel pull-up transistor and an n-channel pull-down transistor, configured with the regulated limiter circuit; however, any predriver arrangement can be configured with the regulated limiter circuit. The regulated limiter circuit can be configured in various manners for limiting or otherwise regulating the maximum gate voltage provided to the gate of the pull-down element to less than the external power supply voltage, without reducing the gate voltage at the minimum voltage specification. For example, the regulated limiter circuit can comprise a single n-channel device, one or more diode-connected p-channel or n-channel transistor devices connected in series, or one or more series connected diode devices, configured to limit or otherwise regulate the gate voltage of the pull-down transistor device.